Modern-day electronics systems typically require multiple patterned layers of electrically or optically active materials, sometimes over a relatively large substrate. Electronics such as radio frequency identification (RFID) tags, photovoltaics, optical sensors, or chemical sensors all require some level of patterning in their electronic circuitry. Flat panel displays, such as liquid crystal displays or electroluminescent displays, typically rely upon accurately patterned sequential layers to form thin film electronic components of a backplane. These electronic components include capacitors, transistors, or power buses. The usual combination of photolithographic patterning methods and selective etch processes has several shortcomings including high cost, difficulty with large substrates, or complexity of selective etch processes.
Feature sizes obtainable using traditional processing methods are limited by the resolution of the photolithography tools. Currently, a minimum feature size for large area display backplanes is around 0.5 microns and requires expensive high end equipment to obtain. Minimum feature sizes for large area substrates using less expensive equipment are usually much larger. High speed circuit operation requires TFTs with high drive current, and many applications also require the drive current be obtained with low voltage operation. It is well known that TFT performance is improved by reducing channel length. In order to move beyond the exposure limitation of feature size, vertical transistors of various architectures are currently being studied. In a vertical TFT architecture, a channel is formed perpendicular to the substrate, and therefore the channel length (L) can be controlled by the height of a layer in the transistor.
Recent work in the fabrication of VTFT, while yielding short channel length devices, uses otherwise standard photolithographic techniques with complex semiconductor processes. For example, since it is not currently possible to put patterns directly on walls which are vertical with respect to a substrate surface, vertical wall patterning has been accomplished using a suitable filler material to partially fill in a trench. The filler material acts as a mask for the portions of the wall located underneath while allowing for processing of the walls above the filler material. This has been used, for example, when an oxide is to be deposited exclusively on vertical walls below a filler material. The oxide is first deposited or produced over the entire surface of the relief. The relief, or trench, is initially completely filled with a suitable filler material. Then, the filler material is recessed back to a depth that just covers the desired oxide. After uncovered sections of the oxide are removed, the remaining filler material is removed.
Alternatively, when it is necessary that an oxide be deposited or produced only in upper regions of a vertical wall, an etching stop layer, for example, a nitride layer, is first provided over the entire surface of the entire relief pattern. A different material, susceptible to directional etching, for example, polycrystalline silicon, is used to fill the relief and is etched back as far as the desired coverage depth of the final vertical oxide. After the etching stop layer is removed from the unfilled sections of the walls, an oxide is deposited or generated using a thermal technique in the uncovered regions. Next, the oxide is anisotropically etched which removes the deposited oxide from horizontal. This is followed by removal of the filler material and, then, the removal of the etching stop layer.
Accordingly, there is an ongoing need to provide semiconductor device architectures that include patterned vertical or inclined device surfaces. There is also an ongoing need to provide simple manufacturing techniques capable of processing small device features of semiconductor devices without requiring high resolution alignments and small gap printing for vertical TFTs. There is also an ongoing need to provide higher current semiconductor devices by improving the series resistance of the device.
In order to maintain acceptable device performance when shrinking the size of a TFT channel, it is typical to scale the layer thicknesses with the size of the device. For example, conventional CMOS production with channel lengths of 90 nm and lower often utilizes dielectric layer thicknesses of less than 10 nm. While there are many processes to deposit dielectric materials, few result in quality films at these thicknesses.
Atomic layer deposition (ALD) is a process that is both conformal and known to result in high quality thin layers when used with optimized process conditions. In ALD processes, typically, two molecular precursors are introduced into the ALD reactor in separate stages. U.S. Patent Application Publication 2005/0084610 (Selitser) discloses an atmospheric pressure atomic layer chemical vapor deposition process that involve separate chambers for each stage of the process and a series of separated injectors are spaced around a rotating circular substrate holder track. A spatially dependent ALD process can be accomplished using one or more of the systems or methods described in more detail in WO 2008/082472 (Cok), U.S. Patent Application Publications 2008/0166880 (Levy), 2009/0130858 (Levy), 2009/0078204 (Kerr et al.), 2009/0051749 (Baker), 2009/0081366 (Kerr et al.), and U.S. Pat. No. 7,413,982 (Levy), U.S. Pat. No. 7,456,429 (Levy), and U.S. Pat. No. 7,789,961 (Nelson et al.), U.S. Pat. No. 7,572,686 (Levy et al), the disclosures of which are hereby incorporated by reference in their entirety.
There is growing interest in combining ALD with a technology known as selective area deposition (SAD). As the name implies, selective area deposition involves treating a portion(s) of a substrate such that a material is deposited only in those areas that are desired, or selected. Sinha et al. (J. Vac. Sci. Technol. B 24 6 2523-2532 (2006)), have remarked that selective area ALD requires that designated areas of a surface be masked or “protected” to prevent ALD reactions in those selected areas, thus ensuring that the ALD film nucleates and grows only on the desired unmasked regions. It is also possible to have SAD processes where the selected areas of the surface area are “activated” or modified in such a way that the film is deposited only on the activated areas. There are many potential advantages to selective area deposition techniques, such as eliminating an etch process for film patterning, reduction in the number of cleaning steps required, or patterning of materials which are difficult to etch. One approach to combining patterning and depositing the semiconductor is shown in U.S. Pat. No. 7,160,819 entitled “METHOD TO PERFORM SELECTIVE ATOMIC LAYER DEPOSITION OF ZINC OXIDE” by Conley et al. Conley et al. discuss materials for use in patterning zinc oxide on silicon wafers. No information is provided, however, on the use of other substrates, or results for other metal oxides.
SAD work to date has focused on the problem of patterning a single material during deposition. There persists a problem of combining multiple SAD steps to form working devices. Processes for building complete devices should be able to control the properties of critical interfaces, particularly in field effect devices like TFTs. There remains a need for processes to simplify the manufacture of vertical TFTs, as well as a need for processes that use SAD and digital patterning processes to pattern devices which have critical vertical features, such as VTFTs. There is also an ongoing need to provide manufacturing techniques that allow the same equipment to deposit multiple, and in some cases all, of the layers making up the electrical components including, for example, conductive layers, insulating layers, or semiconductor layers.